Semiconductor chip layout is subject to complex rules governing, among other things, geometry of shapes on process layers. These complex rules may include, for example, width requirements, spacing requirements, overlap requirements, etc. Compliance with these design rules is important to chip functionality and manufacturability.
Many processes used to create or alter layouts can introduce design rule violations. Manual layout, for example, inevitably introduces violations due to the difficulty of satisfying a large number of complex design rules by hand. These violations are generally corrected via tedious iterations between design rule checking tool runs and manual layout modifications.
Technology migration is another process which gives rise to a large number of design rule violations. Migration is the process, which transforms layouts in one technology to a layout in another technology with different design rules. The migration process begins with scaling, using commercially available programs, and is sufficient to produce a design-rule-correct layout. However, in many cases, non-scalable differences in the design rules result in the introduction of design rules violations, which must again be corrected by tedious manual iteration.
For example, due to the technology difference in technology migration, many library cells grow bigger in terms of pitch. This difference in pitch may potentially create pin mismatches in the new integrated circuit layout. The pin mismatches, if not corrected, may cause the wiring of the integrated circuit to be misaligned.
Conventional layout migration methodology can perform the placement of grown library cells, but does not address the issue of pin mismatches. Specifically, pin mismatches pose a severe challenge in technology migration, which causes difficulty in reusing the wiring connections during layout migration.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.